Matthew Marsicano's Portfolio

Hello, I'm Matthew Marsicano

About Me

I am an Electrical Engineering student at Northeastern University with a passion for ASIC design and silicon engineering, particularly in mixed-signal hardware applications. With a 3.98 GPA and expected graduation in May 2027, I have distinguished myself as an emerging talent in custom silicon development for next-generation consumer products.

My Technical Expertise

My expertise spans silicon design from system-level architecture through layout and verification, utilizing industry-standard tools including Cadence Virtuoso, Magic VLSI, and SKY130 PDK. My hands-on experience includes designing a 40-100MHz PLL ASIC with full schematic capture, layout, and verification through DRC/LVS checks and parasitic simulations. My technical proficiency extends to System Verilog, UVM testbenches, and FPGA implementation, demonstrated through projects like my 16-QAM baseband modulator with comprehensive I/Q imbalance and phase noise analysis.

My Professional Experience

My professional experience reflects my commitment to advancing silicon solutions across diverse applications. At Nokia Bell Labs, I optimized FPGA power consumption by modifying Verilog code for PLL, clock generation, and buffer circuits for backscatter radio systems, while designing 2 PCBs integrating RF, logic analyzer, and power circuits. My automation work reduced testbench PCB bring-up time from 20 minutes to 2 minutes across 300+ devices.

My work at Draper Labs involves testing analog ASICs for power performance and radiation hardness, while my previous role at DEKA Research strengthened my embedded systems expertise with cellular modem architectures and boot optimization.

My Areas of Interest

My particular interest lies in custom silicon for consumer products, low-power wearables, and telecommunications technologies. This focus drives my involvement in cutting-edge projects, from AR headset development with real-time sensor fusion to manufacturing automation systems for international deployment. My leadership role in Northeastern's Generate Product Development Studio showcases my ability to translate silicon-level innovations into market-ready products.

My Recognition & Achievements

Recognition of my potential includes selection as one of only 10 Northeastern students for Apple's Next-gen Innovators program for Hardware Engineers, highlighting my promise in consumer electronics silicon design. My second-place finish at MIT's iQuHack quantum computing hackathon demonstrates my versatility in emerging technologies.