Silicon Projects | Matthew Marsicano

FlashNPU

Designed an on-device neural network accelerator that runs layers straight out of flash with no DRAM.
Weights stream from 4 striped flash channels into a 32-lane INT4 x INT8 weight-streaming GEMV engine. Activations stay in on-chip SRAM.
Layer descriptor sequencer, APB register interface, requantize and output pack, perf counters.
10/10 regression tests bit-exact against a Python golden model. Verilator -Wall lint clean.
Gate-level SKY130 power: 23.6 mW core logic at 100 MHz, about 7 pJ per INT4 MAC, 0.23 mm² of standard cells.
Arty A7 FPGA port in progress.

Differential 8-bit, 1 MS/s SAR ADC with monotonic-switching cap DAC, top-plate sampling, and a PMOS StrongARM comparator.
Built a Python golden model with mismatch Monte Carlo, kT/C, and comparator noise. 7.9 ENOB, DNL p99 0.21 LSB.
Bootstrapped NMOS sampling switch hits 78 dB SFDR in ngspice.
Redesigning the comparator as a double-tail to cut offset.

Digital baseband and RF switch controller for a BLE advertising-channel backscatter tag.
Builds the BLE PDU on the fly (preamble, access address, CRC-24, whitening) with no full-packet buffer. SPI host interface and streaming payload FIFO.
Drives a 4-phase SSB or 2-phase DSB switch pattern, selectable at runtime.
11 cocotb tests bit-exact against a Python golden model. Full P&R in a 1x2 tile at 64 MHz with +3.08 ns setup slack and 0 DRC/LVS errors.

Code Link budget tool

Designed a 40-100 MHz PLL using the SKY130 PDK with custom schematic and layout.
Verified through DRC/LVS and parasitic extraction using ngspice, Xschem, Magic VLSI, and KLayout.